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  rev.2.00, jul.16.2004, page 1 of 7 hd74ac259 8-bit addressable latch rej03d0264?0200z (previous ade-205-385 (z)) rev.2.00 jul.16.2004 description the hd74ac259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. it is a multifunctional device capable or storing single line data in eight addressable latches, and also a 1-of-8 decoder and demultiplexer with active high outputs. the device also incorporates an active low common clear for resetting all latches, as well as an active low enable. features ? serial-to-parallel conversion ? eight bits of storage with output of each bit available ? random (addressable) data entry ? active high demultiplexing or decoding capability ? easily expandable ? common clear ? outputs source/sink 24 ma ? ordering information part name package type package code package abbreviation taping abbreviation (quantity) hd74ac259fpel sop-16 pin (jeita) fp-16dav fp el (2,000 pcs/reel) HD74AC259RPEL sop-16 pin (jedec) fp-16dnv rp el (2,500 pcs/reel) notes: 1. please consult the sales office for the above package availability. 2. the packages with lead-free pins are distinguished from the conventional products by adding v at the end of the package code. pin arrangement 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 a 0 a 1 a 2 q 0 q 1 q 3 q 2 gnd v cc mr e d q 7 q 6 q 5 q 4 (top view)
hd74ac259 rev.2.00, jul.16.2004, page 2 of 7 logic symbol a 0 a 1 a 2 mr q 0 q 1 q 2 ed q 3 q 4 q 5 q 6 q 7 pin names a 0 ? a 2 address inputs d data inputs e enable input (active low) mr master reset (active low) q 0 ? q 7 latch outputs
hd74ac259 rev.2.00, jul.16.2004, page 3 of 7 logic diagram mr a 2 a 1 a 0 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 d e
hd74ac259 rev.2.00, jul.16.2004, page 4 of 7 function table inputs outputs operating mode mr mr mr mr e e e e da 0 a 1 a 2 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 master reset l h x x x x l l l l l l l l demultiplex lldlllq = dl l l l l l l (active high lldhlll q = dl l l l l l decoder when lldlhll l q = dl l l l l d = h) lldhhll l l q = dl l l l lldllhl l l l q = dl l l lldhlhl l l l l q = dl l lldlhhl l l l l l q = dl lldhhhl l l l l l l q = d store (do nothing) h h x x x x q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 addressable latch h l d l l l q = d q 1 q 2 q 3 q 4 q 5 q 6 q 7 hldhllq 0 q = d q 2 q 3 q 4 q 5 q 6 q 7 hldlhlq 0 q 1 q = d q 3 q 4 q 5 q 6 q 7 hldhhlq 0 q 1 q 2 q = d q 4 q 5 q 6 q 7 hldllhq 0 q 1 q 2 q 3 q = d q 5 q 6 q 7 hldhlhq 0 q 1 q 2 q 3 q 4 q = d q 6 q 7 hl d l hhq 0 q 1 q 2 q 3 q 4 q 5 q = d q 7 hl d hhhq 0 q 1 q 2 q 3 q 4 q 5 q 6 q = d h : high voltage level l : low voltage level x : immaterial d : high or low data one setup time prior to the low-to-high enable transition. q : lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared. absolute maximum ratings item symbol ratings unit condition supply voltage v cc ?0.5 to 7 v ?20 ma v i = ?0.5v dc input diode current i ik 20 ma v i = vcc+0.5v dc input voltage v i ?0.5 to vcc+0.5 v ?50 ma v o = ?0.5v dc output diode current i ok 50 ma v o = vcc+0.5v dc output voltage v o ?0.5 to vcc+0.5 v dc output source or sink current i o 50 ma dc v cc or ground current per output pin i cc , i gnd 50 ma storage temperature tstg ?65 to +150 c recommended operating conditions item symbol ratings unit condition supply voltage v cc 2 to 6 v input and output voltage v i , v o 0 to v cc v operating temperature ta ?40 to +85 c v cc = 3.0v v cc = 4.5 v input rise and fall time (except schmitt inputs) v in 30% to 70% v cc tr, tf 8 ns/v v cc = 5.5 v
hd74ac259 rev.2.00, jul.16.2004, page 5 of 7 dc characteristics ta = 25 c ta = ?40 to +85 c item sym- bol vcc (v) min. typ. max. min. max. unit condition 3.0 2.1 1.5 ? 2.1 ? 4.5 3.15 2.25 ? 3.15 ? v ih 5.5 3.85 2.75 ? 3.85 ? v out = 0.1 v or v cc ?0.1 v 3.0 ? 1.50 0.9 ? 0.9 4.5 ? 2.25 1.35 ? 1.35 input voltage v il 5.5 ? 2.75 1.65 ? 1.65 v v out = 0.1 v or v cc ?0.1 v 3.0 2.9 2.99 ? 2.9 ? 4.5 4.4 4.49 ? 4.4 ? 5.5 5.4 5.49 ? 5.4 ? v in = v il or v ih i out = ?50 a 3.0 2.58 ? ? 2.48 ? i oh = ?12 ma 4.5 3.94 ? ? 3.80 ? i oh = ?24 ma v oh 5.5 4.94 ? ? 4.80 ? v in = v il or v ih i oh = ?24 ma 3.0 ? 0.002 0.1 ? 0.1 4.5 ? 0.001 0.1 ? 0.1 5.5 ? 0.001 0.1 ? 0.1 v in = v il or v ih i out = 50 a 3.0 ? ? 0.32 ? 0.37 i ol = 12 ma 4.5 ? ? 0.32 ? 0.37 i ol = 24 ma output voltage v ol 5.5 ? ? 0.32 ? 0.37 v v in = v il or v ih i ol = 24 ma input leakage current i in 5.5 ? ? 0.1 ? 1.0 av in = v cc or gnd i old 5.5???86?mav old = 1.1 v dynamic output current * i ohd 5.5 ? ? ? ?75 ? ma v ohd = 3.85 v quiescent supply current i cc 5.5 ? ? 8.0 ? 80 av in = v cc or ground * maximum test duration 2.0 ms, one output loaded at a time. ac characteristics ta = +25c c l = 50 pf ta = ?40c to +85c c l = 50 pf item symbol v cc (v) * 1 min typ max min max unit maximum clock f max 3.3 65 ? ? 60 ? mhz frequency 5.0 110 ? ? 95 ? propagation delay t phl 3.3 1.0 8.5 14.5 1.0 16.5 ns mr to q n 5.0 1.0 6.5 9.0 1.0 10.5 propagation delay t plh 3.3 1.0 7.0 10.5 1.0 12.0 ns d n to q n 5.0 1.0 5.5 7.5 1.0 8.5 propagation delay t phl 3.3 1.0 7.0 10.5 1.0 12.0 ns d n to q n 5.0 1.0 5.5 7.5 1.0 8.5 propagaion delay t plh 3.3 1.0 11.5 18.5 1.0 21.5 ns a n to q n 5.0 1.0 8.0 11.5 1.0 14.0 propagation delay t phl 3.3 1.0 11.5 18.5 1.0 21.0 ns a n to q n 5.0 1.0 8.0 11.5 1.0 13.5 propagation delay t plh 3.3 1.0 9.0 15.0 1.0 17.0 ns e to q 5.0 1.0 6.5 9.0 1.0 10.5 propagation delay t phl 3.3 1.0 9.0 14.0 1.0 16.0 ns e to q n 5.0 1.0 6.5 8.5 1.0 10.0 note: 1. voltage range 3.3 is 3.3 v 0.3 v voltage range 5.0 is 5.0 v 0.5 v
hd74ac259 rev.2.00, jul.16.2004, page 6 of 7 ac operating requirements ta = +25c c l = 50 pf ta = ?40c to +85c c l = 50 pf item symbol v cc (v) * 1 typ guaranteed minimum unit setup time, high or low t su 3.3 1.0 3.5 3.5 ns d to e 5.0 0.0 3.0 3.0 hold time, high or low t h 3.3 0.5 2.0 2.0 ns d to e 5.0 0.5 2.0 2.0 setup time, high or low t su 3.3 1.0 6.0 7.0 ns a n to e 5.0 0.0 4.5 5.0 hold time, high or low t h 3.3 ?3.0 0.0 0.0 ns a n to e 5.0 ?1.0 0.0 0.0 pulse width t w 3.3 3.0 5.5 7.0 ns 5.0 3.0 4.5 5.0 note: 1. voltage range 3.3 is 3.3 v 0.3 v voltage range 5.0 is 5.0 v 0.5 v capacitance item symbol typ unit condition input capacitance c in 4.5 pf v cc = 5.5 v power dissipation capacitance c pd 35 pf v cc = 5.0 v
hd74ac259 rev.2.00, jul.16.2004, page 7 of 7 package dimensions package code jedec jeita mass (reference value) fp-16dav ? conforms 0.24 g *ni/pd/au plating *0.20 ?0.05 *0.40 ?0.06 0.12 0.15 m 2.20 max 5.5 10.06 0.80 max 16 9 1 8 10.5 max + 0.20 ? 0.30 7.80 0.70 ?0.20 0 ? ?8 ? 0.10 ?0.10 1.15 1.27 as of january, 2003 unit: mm package code jedec jeita mass (reference value) fp-16dnv conforms conforms 0.15 g *ni/pd/au plating 1.27 16 9 1 8 0.15 0.25 m 1.75 max 3.95 *0.20 0.05 9.9 0 ? 8 ? 10.3 max + 0.10 0.30 6.10 + 0.67 0.20 0.60 + 0.11 0.04 0.14 *0.40 0.06 0.635 max 1.08 as of january, 2003 unit: mm
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices ? 200 4. re nesas technology corp ., all rights reser v ed. printed in ja pan. colophon .1.0


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